Nowadays, dynamic random access memories (DRAMs) are the highest volume production semiconductor devices. Because of their high integration level and relatively low power consumption, DRAMs have become the mainstay in many computer applications although they have more complex circuitry required to read, write, and refresh the data. Additionally, the adoption of DRAMs has greatly increased the amount of data that can be stored per unit area in memory cells. The advantages of low cost and high integration have the industry moved toward intense development of DRAMS.
In DRAMs, the sense amplifiers are designed for the read/write operation of each location of memory cells. DRAM cells are connected to sense amplifiers, which sense the voltage of the capacitors in the DRAM cells and compare the sensing voltages with a reference voltage in the sense amplifier. In this process, the content of the memory can be determined. The data contained in a DRAM cell, however, may be undetermined after a read/write operation, therefore, a refresh operation should apply therein.
One of the major concerns in the architecture of DRAMs is power consumption. DRAMs will continue moving to lower voltages driven by technology. For example, one of the specifications of the design of modern DRAMs is "power down active", which sets a limit for the power dissipation of DRAM chips.
For transistor reliability concerns, an on-chip voltage down converter (regulator) is used to maintain the external voltage level while providing a lower voltage across the memory cells in order to reduce the hot electron effect. In modern memory design, it is not unusual to have more than two regulated powers for the periphery circuitry and the bit line sense amplifier. However, the regulators always consume a large amount of DC current regardless whether they are operating or not.
In general, there is no power down (cut off) control on the regulated sense amplifier or the existing power down schemes do not meet the requirements of modern memory design specifications. One example of those schemes is that the time duration is set to be fixed for providing over time for the sense amplifier. In such a case, the power consumption could be too much, and the current variation and higher temperature are still arduous problems which need to be solved. Therefore, a smart power down scheme to turn off the Vcc of the bit line sense amplifier (Vccsa), thus reducing DC power consumption to a large extent, has to be developed.